awlevin/WiscArchitecture
A fully functional processor with a proprietary instruction set architecture.
Verilog
Issues
- 0
- 1
Different shift modules
#2 opened by awlevin - 3
Ensure proper reg and mem writes
#7 opened by lmiller36 - 0
- 0
- 0
Fix flags in same cycle for branching
#6 opened by lmiller36 - 0
Pipelining
#5 opened by awlevin - 0
PADDSB off by 1 problem
#1 opened by awlevin