Pinned Repositories
AXI4_Lite_adapters
Design and verification Verilog/SystemVerilog modules for a pair of AXI4 Lite adapters.
HCoEthernet
Some of the software/hardware developed throughout my HCoE final project. Work in progress.
SV-interface-gen
Python script to generate SystemVerilog interfaces with clocking blocks and async ports from a list of signals.
xsim_bash
Shell script to automate Vivado sim for (System)Verilog testbench + DUT
b-arar's Repositories
b-arar/HCoEthernet
Some of the software/hardware developed throughout my HCoE final project. Work in progress.
b-arar/AXI4_Lite_adapters
Design and verification Verilog/SystemVerilog modules for a pair of AXI4 Lite adapters.
b-arar/xsim_bash
Shell script to automate Vivado sim for (System)Verilog testbench + DUT
b-arar/SV-interface-gen
Python script to generate SystemVerilog interfaces with clocking blocks and async ports from a list of signals.