RISCV32 Support

[BijanT]

I would like to run FeRTOS on a RISCV processor. Looking at the list of architectures rust targets riscv32imac-unknown-none-elf might be what we want to target first. Then, we can see if riscv64gc/imac support is something we could easily add.
This will also involve refactoring the code because there is a lot of architecture specific code in the task module as well as the interrupt module. I would recommending making a new directory called arch and then have directories in there for each architecture. For example, the file tree might look something like:

• src
  • arch
    • arm
      • task.rs
      • interrupt.rs
    • riscv
      • task.rs
      • interrupt.rs

and then you would be able to conditionally compile to use in the rest of the code

We would also add another example project using riscv as a target.