baimengwei

baimengwei's Stars

• vnpy/vnpy

  基于Python的开源量化交易平台开发框架

  Language:Python24.4k8.6k

• misc0110/PTEditor

  A small library to modify all page-table levels of all processes from user space for x86_64 and ARMv8.

  Language:C22969

• gpgpu-sim/gpgpu-sim_distribution

  GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.

  Language:C++1.1k500

• YosysHQ/yosys

  Yosys Open SYnthesis Suite

  Language:C++3.4k871

• Shougo/echodoc.vim

  Print documents in echo area.

  Language:Vim Script57732

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.7k501

• bootlin/elixir

  The Elixir Cross Referencer

  Language:C962141

• tjeznach/linux

  Linux kernel source tree

  Language:C910

• riscv-software-src/riscv-perf-model

  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

  Language:C++12854

• taichi-ishitani/tvip-axi

  AMBA AXI VIP

  Language:SystemVerilog350102

• mortbopet/Ripes

  A graphical processor simulator and assembly editor for the RISC-V ISA

  Language:C++2.5k270

• chipsalliance/verible

  Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

  Language:C++1.3k199

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.2k670

• gem5/gem5

  The official repository for the gem5 computer-system architecture simulator.

  Language:C++1.6k1.2k

• fabmen/asciidoctor-graph

  Language:Ruby1

• Eugnis/spectre-attack

  Example of using revealed "Spectre" exploit (CVE-2017-5753 and CVE-2017-5715)

  Language:C755170

• riscv-non-isa/iopmp-spec

  This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

  Language:Makefile6

• riscv-boom/boom-attacks

  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)

  Language:C5916

• riscv/riscv-opcodes

  RISC-V Opcodes

  Language:Python668293

• lancetw/ebook-1

  A collection of classic computer science books from Internet

  3.7k1.7k

• Paul-Marie/minilibc

  minilibc Minilibc MinilibC MiniLibC MINILIBC

  Language:C202

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog920409

• QSCTech/zju-icicles

  浙江大学课程攻略共享计划

  Language:HTML36.9k9.4k

• PyHDI/Pyverilog

  Python-based Hardware Design Processing Toolkit for Verilog HDL

  Language:Python613169

• qemu/qemu

  Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

  Language:C10.1k5.5k

• runninglinuxkernel/riscv_programming_practice

  Language:C16955

• mnurzia/rv

  32-bit RISC-V CPU in ~800 lines of C89

  Language:C60328

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3k745

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k281

• Dmitriy0111/nanoFOX

  A small RISC-V core (SystemVerilog)

  Language:SystemVerilog282