basemhesham

32-bit_single_cycle_MIPS_processor

basemhesham

Design-and-ASIC-Implementation-of-UART

This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II

Digital-Design-of-FIR-Filter-Transposed-Structure

Design and Validation of a Customizable 50th-Order Low-Pass FIR Filter. Transitioning from MATLAB Modeling to Verilog RTL Design and simulation Testing.

Verilog_HDL

basemhesham/Design-and-ASIC-Implementation-of-UART

This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II

basemhesham/Digital-Design-of-FIR-Filter-Transposed-Structure

Design and Validation of a Customizable 50th-Order Low-Pass FIR Filter. Transitioning from MATLAB Modeling to Verilog RTL Design and simulation Testing.

basemhesham/32-bit_single_cycle_MIPS_processor

basemhesham/basemhesham

basemhesham/Verilog_HDL