/voyager-cpu

A simple Python emulation a 32-bit RISC-V CPU

Primary LanguagePythonMIT LicenseMIT

voyager-cpu

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Voyager is a (very) experimental Python emulator of a 32-bit RISC-V core. It's built for research and education with simplicity in mind.

Features

  • Supports the RV32I ISA using a non-pipelined CPU with a single-cycle instruction fetch, decode, and execution stage.
  • A simple virtual RAM into which test programs (ELF binaries) are loaded.
  • A basic REPL for viewing register and RAM contents, and executing the next N cycles.
  • MIT license.

Build and Run

  1. Clone the repository.
  2. (Optional) Clone the pre-built RV32UI tests using:
git submodule init
git submodule update

The binaries will be placed under tests/riscv-tests-prebuilt-binaries/. Alternatively, you can build the test suites from the official repo.

  1. See the example in src/voyagercpu/example.py. You may run this directly using python src/voyagercpu/example.py.

  2. Enjoy!

  3. (Optional) Run the Voyager unit tests using pytest

Todo

  • Add more tests, particularly at the execution stage.
  • Implement some ISA extensions, e.g. the M and C specifications.
  • Add pipelining and privileged mode.
  • Improve pretty printing.
  • Etc.

Please contribute!