Generate Verilog register model from compiled SystemRDL input
Install from pypi:
pip3 install peakrdl-verilog
Install from github:
pip3 install git+https://github.com/bat52/PeakRDL-verilog.git@master
Pass the elaborated output of the SystemRDL Compiler to the exporter.
import sys
from systemrdl import RDLCompiler, RDLCompileError
from peakrdl.verilog import VerilogExporter
rdlc = RDLCompiler()
try:
rdlc.compile_file("path/to/my.rdl")
root = rdlc.elaborate()
except RDLCompileError:
sys.exit(1)
exporter = VerilogExporter()
exporter.export(root, "test.sv")
The tool will generate a tb for your module in the same directory. This will test the HW interface
Constructor for the Verilog Exporter class
Optional Parameters
user_template_dir
- Path to a directory where user-defined template overrides are stored.
user_template_context
- Additional context variables to load into the template namespace.
Perform the export!
Parameters
node
- Top-level node to export. Can be the top-level
RootNode
or any internalAddrmapNode
.
- Top-level node to export. Can be the top-level
path
- Output file.
Optional Parameters