beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA

That is a design a floating point multiplier based in the ieee standard 764 using vhdl and it has been implemented in the FPGA Cyclone II

FLOATING-POINT-MULTIPLIER-USING-FPGA

That is a design a floating point multiplier based in the ieee standard 764 using vhdl and it has been implemented in the FPGA Cyclone II

The project Authors are :

Mohamed Beltagy email:mohamed.beltagy@usi.ch

Andrés Felipe Valencia email:valena@usi.ch

here is a link to the video of the project https://www.youtube.com/watch?v=xYQko8mupK0