bhrigub/DFF-with-asynchronous-preset-and-reset-and-verified-for-Xilinx-Virtex-6-FPGA
DFF with asynchronous preset and reset and verified for Xilinx Virtex 6 FPGA
Verilog
No issues in this repository yet.
DFF with asynchronous preset and reset and verified for Xilinx Virtex 6 FPGA
Verilog
No issues in this repository yet.