An ASIC designed under cell-based design flow. Developed by MATLAB for algorithm specification, by Verilog for RTL work, by Synopsys Design Compiler for logic synthesis, by Innovus for Place & Route, and taped out by CIC.
binzheng305/SVD_CHIP
An ASIC designed under cell-based design flow. Developed by MATLAB for algorithm specification, by Verilog for RTL work, by Synopsys Design Compiler for logic synthesis, by Innovus for Place & Route, and taped out by CIC.
Verilog