Pinned Repositories
-Designing-Hexagonal-Architecture-with-Java---Second-Edition
Designing Hexagonal Architecture with Java - Second Edition, Published by Packt
16-Bit-CPU-using-Verilog
Design of a 16-Bit CPU using Verilog
1backend
Run your web apps easily with a complete platform that you can install on any server. Build composable microservices and lambdas.
2020-02-sacon-nyc
content repository for 2020-02 SaCon NYC edition of "Design and Build Great APIs"
8-bit-ALU-in-verilog
8-bit ALU in Verilog.
8-bit_fpga_cpu
An 8-Bit CPU implemented in an FPGA
8bit-computer
A simple 8-bit computer build in Verilog.
8bit_MicroComputer_Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
Hello-World
My First Project
Spoon-Knife
This repo is for demonstration purposes only. Comments and issues may or may not be responded to.
blaizedsouza's Repositories
blaizedsouza/8bit-computer
A simple 8-bit computer build in Verilog.
blaizedsouza/amaranth
A modern hardware definition language and toolchain based on Python
blaizedsouza/Arduino
ESP8266 core for Arduino
blaizedsouza/arduino-esp32
Arduino core for the ESP32
blaizedsouza/ArduinoCore-API
Hardware independent layer of the Arduino cores defining the official API
blaizedsouza/ArduinoCore-avr
The Official Arduino AVR core
blaizedsouza/Asynchronous-Programming-in-Rust
Asynchronous Programming in Rust, published by Packt
blaizedsouza/Bare-Metal-Embedded-C-Programming
Bare-Metal Embedded C Programming by Packt Publishing
blaizedsouza/Building-LLM-Powered-Applications
Building Large Language Model Applications, Published by Packt
blaizedsouza/Building-Resilient-Architectures-on-AWS
Building Resilient workload on AWS, published by Packt
blaizedsouza/cii
C Interfaces and Implementations
blaizedsouza/Digital
A digital logic designer and circuit simulator.
blaizedsouza/effective-c
book notes for "Effective C" by Robert C. Seacord
blaizedsouza/GraphQL-Best-Practices
GraphQL Best Practices, published by Packt
blaizedsouza/HOLY_CORE_COURSE
Learn how to build our own RV32I core and use it on FPGA.
blaizedsouza/Java-21-Exploring-the-Latest-Innovations-for-2024
blaizedsouza/Java-Concurrency-and-Parallelism
Parallel Programming and Concurrency in Java, published by Packt
blaizedsouza/Kubernetes-An-Enterprise-Guide-Third-Edition
Kubernetes – An Enterprise Guide, Third Edition - Published by Packt
blaizedsouza/Learn-to-Code-with-Rust
blaizedsouza/LLM-Engineers-Handbook
The LLM's practical guide: From the fundamentals to deploying advanced LLM and RAG apps to AWS using LLMOps best practices
blaizedsouza/logisim-evolution
Digital logic design tool and simulator
blaizedsouza/Modern-Network-Observability
Reference Lab and Observability architecture that accompanies the book
blaizedsouza/Modern-Reverse-Engineering-Docs
Modern Reverse Engineering books and resources
blaizedsouza/Platform-Engineering-for-Architects
Platform Engineering for Architects, published by Packt
blaizedsouza/Programming-Massively-Parallel-Processors
blaizedsouza/RAG-Driven-Generative-AI
This repository provides programs to build Retrieval Augmented Generation (RAG) code for Generative AI with LlamaIndex, Deep Lake, and Pinecone leveraging the power of OpenAI and Hugging Face models for generation and evaluation.
blaizedsouza/rvalp
RISC-V Assembly Language Programming
blaizedsouza/teahouse
Sample applications to demonstrate Observability concepts
blaizedsouza/Unlocking-Data-with-Generative-AI-and-RAG
Unlocking Data with Generative AI and RAG, published by Packt
blaizedsouza/zipcpu
A small, light weight, RISC CPU soft core