blegal

INRIA & IRISA lab. (ENSSAT)Lannion, FRANCE

Pinned Repositories

ADMM_LDPC_decoder_on_GPU
An ADMM LDPC decoder implemented on GPU device
Language:C64
ADMM_parameter
A program to compute the ADMM-l1 coefficents for LDPC decoding
Language:C++4 3 03
AVX2_shift_and_rotate_si256
The missing _mm256_slli_si256, _mm256_srli_si256, , _mm256_rol_si256 and _mm256_ror_si256 functions
Language:C++30
EN224-Test-et-verification
Digital design verification lesson provided at ENSEIRB-MATMECA school
Language:C++4 2 022
EN325-Advanced-digital-design-old
Language:C++72
Fast_LDPC_decoder_for_ARM15
LDPC decoders for ARM processor
Language:C10 3 04
Fast_LDPC_decoder_for_GPU_fixed
High-throughput LDPC decoder on GPU device (see published IEEE article)
Language:C105
Fast_LDPC_decoder_for_GPU_float
High-throughput LDPC decoder on GPU device (see IEEE journal publication)
Language:C62
Fast_LDPC_decoder_for_x86
The source codes of the fast x86 LDPC decoder published
Language:C24 7 412
JPEG_4_HLS
Description of a JPEG encoder for Vivado HLS tool
Language:C++7 2 11

blegal's Repositories

blegal/Fast_LDPC_decoder_for_x86
The source codes of the fast x86 LDPC decoder published
Language:C24 7 412
blegal/Fast_LDPC_decoder_for_ARM15
LDPC decoders for ARM processor
Language:C10 3 04
blegal/Fast_LDPC_decoder_for_GPU_fixed
High-throughput LDPC decoder on GPU device (see published IEEE article)
Language:C105
blegal/EN325-Advanced-digital-design-old
Language:C++72
blegal/Fast_LDPC_decoder_for_GPU_float
High-throughput LDPC decoder on GPU device (see IEEE journal publication)
Language:C62
blegal/EN224-Test-et-verification
Digital design verification lesson provided at ENSEIRB-MATMECA school
Language:C++4 2 022
blegal/AVX2_shift_and_rotate_si256
The missing _mm256_slli_si256, _mm256_srli_si256, , _mm256_rol_si256 and _mm256_ror_si256 functions
Language:C++30
blegal/adsb-like-comm-toolbox
Language:VHDL12
blegal/ENSSAT-SNum2-Test-and-Verification
Language:C++1
blegal/HLS-Sorter-on-FPGA
An example of Vitis HLS design flow from C/C++ code down to FPGA device (Nexys 4 with UART link)
Language:VHDL1 1 0
blegal/Mandelbrot-SIMD-and-GPU
Language:C++1
blegal/pg208_draw_project
The source code provided for pg208 project (drawing tool)
Language:C++1 2 03
blegal/pg208_web_project
The source code provided for pg208 project (QT web server)
Language:C++11
blegal/adsb-observer
Language:C++
blegal/adsb-receiver
Language:C++
blegal/AVX2_float_functions
Language:C++
blegal/blegal.github.io
Language:VHDL
blegal/bqf_genric_functions
Language:C++
blegal/EN201_UARTLoader
Language:C++1 0
blegal/EN325-Advanced-digital-design
Language:C++3
blegal/french_word_sudent
Language:C
blegal/hl5
A 32-bit RISC-V Processor Designed with High-Level Synthesis
blegal/HLS-Sorter-on-FPGA-int32_t
An example of Vitis HLS design flow from C/C++ code down to FPGA device (Nexys 4 with UART link + data packing)
Language:C++
blegal/hls_sinus_and_cosinus
Language:C++
blegal/intfftk
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Language:VHDL2 0
blegal/pg208_bibliotheque
Language:C++
blegal/SE301-GalaxEirb-Student
Language:C++1
blegal/SE301-High-Performance-Computing-Student
Language:C++
blegal/SFML-simple-maze
Language:C++2 0
blegal/SIMD_bitset_rotation
Language:C++