bmindur

Pinned Repositories

myhdl
The MyHDL development repository
Language:Python00
verilog-axi
Verilog AXI components for FPGA implementation
Language:Verilog00
verilog-axis
Verilog AXI stream components for FPGA implementation
Language:Python00
verilog-ethernet
Verilog Ethernet components for FPGA implementation
Language:Verilog00
verilog-i2c
Verilog I2C interface for FPGA implementation
Language:Verilog00
verilog-lfsr
Fully parametrizable combinatorial parallel LFSR/CRC module
Language:Verilog00
verilog-uart
Verilog UART
Language:Verilog00
viv-prj-gen
tcl scripts used to build or generate vivado projects automatically
Language:CMake00

bmindur's Repositories

bmindur/myhdl
The MyHDL development repository
Language:Python00
bmindur/verilog-axi
Verilog AXI components for FPGA implementation
Language:Verilog00
bmindur/verilog-axis
Verilog AXI stream components for FPGA implementation
Language:Python00
bmindur/verilog-ethernet
Verilog Ethernet components for FPGA implementation
Language:Verilog00
bmindur/verilog-i2c
Verilog I2C interface for FPGA implementation
Language:Verilog00
bmindur/verilog-lfsr
Fully parametrizable combinatorial parallel LFSR/CRC module
Language:Verilog00
bmindur/verilog-uart
Verilog UART
Language:Verilog00
bmindur/viv-prj-gen
tcl scripts used to build or generate vivado projects automatically
Language:CMake00