Verilog HDL code of Eric SoC : SoC, PCIe end point, pattern matching co processor sources/cores/mpu/ Pattern matchin co processor implementation sources/cores/hm/ Transactional layer of PCIe endpoint : DMA management; BAR management; expansion ROM management. sources/cores/wb_emac/ Ethernet mac adapted from Milkymist sources/cores/trn/ Xilinx PCIe IP core wishbone wrapper bram/ Wishbone SRAM slave based on internal FPGA RAM blocks