bolifeyo

5-Stage_RISC-V_Processor

Worked on a team of 3 to complete a pipelined RISC-V processor from scratch in System Verilog, complete with dual L1 Caches, a L2 cache, prefetching, and a branch predictor.

AdderNet

Code for paper " AdderNet: Do We Really Need Multiplications in Deep Learning?"

alpha-zero-general

A clean implementation based on AlphaZero for any game in any framework + tutorial + Othello/Gobang/TicTacToe/Connect4

ARM_AMBA_Design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

armv7m-emulator

An ARMv7-M emulator, written in Go

axi4-interface

AXI4 and AXI4-Lite interface definitions

buildYOLO

젯슨나노에서 YOLO v3 (GPU + CUDNN + OpneCV 전용) 설치하기

cmake-examples

Useful CMake Examples

Computer-Architecture

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

confmc.examples

CON-FMC Examples for Version 2019.05

bolifeyo/AdderNet

Code for paper " AdderNet: Do We Really Need Multiplications in Deep Learning?"

bolifeyo/ARM_AMBA_Design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

bolifeyo/cmake-examples

Useful CMake Examples

bolifeyo/Computer-Architecture

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

bolifeyo/darknet_ros

YOLO ROS: Real-Time Object Detection for ROS

bolifeyo/Data-Structures-and-Algorithms-Python

All the essential resources and template code needed to understand and practice data structures and algorithms in python with few small projects to demonstrate their practical application.

bolifeyo/databook_python

IPython notebooks with demo code intended as a companion to the book "Data-Driven Science and Engineering: Machine Learning, Dynamical Systems, and Control" by Steven L. Brunton and J. Nathan Kutz

bolifeyo/deep_sort_pytorch

MOT tracking using deepsort and yolov3 with pytorch

bolifeyo/EmojiRecommend

소웨지존 팀, 이모티콘 추천 분류기 (2019)

bolifeyo/FKP

Official PyTorch code for Flow-based Kernel Prior with Application to Blind Super-Resolution (FKP), CVPR2021

bolifeyo/Hazard3

3-stage RV32IMACZb* processor with debug

bolifeyo/hf-risc

HF-RISC SoC

bolifeyo/kronos

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

bolifeyo/libtorch-yolov5

A LibTorch inference implementation of the yolov5

bolifeyo/mmRISC-1

RISC-V RV32IMAFC Core for MCU

bolifeyo/ModooCode

Repo for the Modoocode.

bolifeyo/nvdla-parser

A NVDLA Loadable Parser.

bolifeyo/Pruned-YOLO

Using model pruning method to obtain compact models Pruned-YOLOv5 based on YOLOv5.

bolifeyo/Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

bolifeyo/riscv-simple

Computer architecture learning environment using FPGAs

bolifeyo/riscv-simple-sv

A simple RISC V core for teaching

bolifeyo/riscv-z0

RISC-V Z0 - A RISCV32-IMC CORE

bolifeyo/riscv-z1

RISC-V Z1 - A RISCV32-IMCB CORE

bolifeyo/riscv-z3

RISC-V Z3 - A RISCV32-IMCB CORE

bolifeyo/wb2axip

Bus bridges and other odds and ends

bolifeyo/yolov5

YOLOv5 🚀 in PyTorch > ONNX > CoreML > TFLite

bolifeyo/yolov5-pruning

bolifeyo/Yolov5_DeepSort_Pytorch

Real-time multi-object tracker using YOLO v5 and deep sort

bolifeyo/YoloV5sl_V4_prune

YoloV5sl_V4模型pruning

bolifeyo/ZYNQ-NVDLA

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.