bonifus

accelerator-wall

Repository for the tools and non-commercial data used for the "Accelerator wall" paper.

cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

COFFE

FPGA-Accelerator-for-AES-LeNet-VGG16

FPGA/AES/LeNet/VGG16

fpga-ml-accelerator

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

kbdd

keyboard library for per-window keyboard layout

Nathan_SMD.pretty

My SMD footprints for KiCad, mostly untested/verifies use at your own risk

PreAcademy

SH_SOD_SON_SOT.pretty

PRJCT.NET KiCad footprint modules for SO, SOD, SOT, SON, USON, etc

VGG16_FPGA_Accelerator

A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 16 (fp16).

bonifus/cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

bonifus/accelerator-wall

Repository for the tools and non-commercial data used for the "Accelerator wall" paper.

bonifus/COFFE

bonifus/FPGA-Accelerator-for-AES-LeNet-VGG16

FPGA/AES/LeNet/VGG16

bonifus/fpga-ml-accelerator

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

bonifus/kbdd

keyboard library for per-window keyboard layout

bonifus/Nathan_SMD.pretty

My SMD footprints for KiCad, mostly untested/verifies use at your own risk

bonifus/PreAcademy

bonifus/SH_SOD_SON_SOT.pretty

PRJCT.NET KiCad footprint modules for SO, SOD, SOT, SON, USON, etc

bonifus/VGG16_FPGA_Accelerator

A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 16 (fp16).

bonifus/vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

bonifus/zynqnet

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"