- Video DAC ADV7125 (or ADV7123)
- Automatic detection of progressive (240p/288p) and interlaced (480i/576i)
- Automatic detection of NTSC and PAL mode
- VI-DeBlur in 240p/288p
- Horizontal resolution decreased from 640 to 320 pixels removing interpolation pixels in 240p/288p mode and producing a sharper image.
- Please note that not all games outputting 320x240 at progressive scan mode. Some outputting full 640x240 horizontal resolution. Therefor having VI-DeBlur enabled decreases image sharpness in that case.
- 16bit color mode
- Reduces color depth from 21bit (7bit each color) to 16bit (5bit for red and blue and 6bit for green)
- Some games use the LSBs just for inserting some kind of noise, so the 16bit gives you a clearer image.
- IGR features:
- reset the console with the controller
- quick change on VI-DeBlur and 16bit mode with the controller
Three functionalities are implemented: toggle vi-deblur feature and toggle the 16bit mode as well as resetting the console. They are only available if the installation allows you to use these functions. They can be disabled via jumper setting on the modding PCB (see Jumper Setup description in the PCB repository).
The button combination are as follows:
- reset the console: Z + Start + R + A + B
- (de)activate VI-DeBlur:
- deactivate: Z + Start + R + C-le
- activate: Z + Start + R + C-ri
- (de)activate 16bit mode:
- deactivate: Z + Start + R + C-up
- activate: Z + Start + R + C-dw
If you read here and there the abbreviation IGR, this may translate to either In-Game-Reset or In-Game-Routines.
Defaults for VI-DeBlur and 16bit are determined via jumper settings on the N64RGBv2.1 mainboard. As these jumpers are read continuously during runtime you can also toggle their state at runtime. This means a switch soldered to the jumpers allows the user to toggle VI-DeBlur and 16bit mode. Please see the PCB repository for more details on how an installation configuration with switches works.
IMPORTANT NOTE
This firmware is not meant for any of Tim Worthingtons N64RGB board.
I discontinued support for any of his products a few years ago due to reasons.
Use this firmware only and only for my N64RGBv2.1 board!
Thank you.
To update the firmware via JTAG, you need to have:
- an Altera USB Blaster (or clone) for flashing the firmware
- Quartus Prime Programmer software installed on your computer
(Programmer software is offered as stand-alone application; so you don't need to have the whole Quartus Prime suite installed.) - If the programmer driver won't work on your Windows system, please use the following driver: Link to Terasic.com Wiki.
The update procedure is as follows:
- Download the latest firmware from the Github Repository
- Start the Quartus Prime Programmer software
- Select the programmer adapter under Hardware Setup... if not automatically selected
- Add the programming file with Add File...
- Programming file ends with *.pof.
- Programming file is named after PCB version and CPLD, e.g. n64rgbv2_1_5M570ZT100.pof stands for N64RGBv2.1 and 5M570ZT100 CPLD
- Check Program / Configure and Verify for your CPLD devices CFM which should appear with the previous step.
- Click on Start and wait patiently
Please note that the console must be turned on in order to provide a reference target voltage for the programming device.
After cloning the repository, you will find several folders. Here is a description of what to find where. Please note that subfolders are not necessarily outlined.
| Folder | Description |
|---|---|
| doc | Documentation related files (e.g. certain pictures) |
| lib | Verilog header files |
| quartus | Relevant project and revision files for the hardware design |
| rtl | Verilog hardware description files |
| sdc | SDC (Standard Design Constraints or Synopsys Design Constraints) files |
The following instruction does not explain how to use the certain tools and/or to manage your personal design flow. It is meant as a first instruction how to setup the N64Adv development.
These are the software requirements:
- Quartus Prime Lite by intelFPGA (currently version 21.1) with MaxII and MaxV CPLD device support
If not already done, clone the GIT source. Open the project file with Quartus Prime Lite. Afterwards select the revision you like to work with; a quick switch is in the middle of the control/symbol bar. The revision is named after the CPLD you'd like to use / build the firmware for.
There is no need to build any IP-cores as they are not used. You can directly Compile Design (e.g. using the shortcut Ctrl. + L). If everything went correct the design should compile just fine (Warnings are ok).
If you wish to develop with an older PCB version (N64RGBv2 or N64RGB), you have to change the branch to discontinue. Project file for these PCBs will then show up.