Digital Projects made in VHDL for the "Digital Systems" course, using the Zybo board with Zynq 7000 SoC.
Assignments and Finite State Machines (FSM):
- Assignment 1: Logic Gates and Logic Blocks in VHDL.
- Assignment 2: Moore machine FSM in VHDL of a detector of two consecutive pulses.
- Assignment 3: Mealy machine FSM in VHDL of a detector of two consecutive pulses.
- Assignment 4: Project of Various FSM and a rising-edge detector Moore machine FSM in VHDL.
- Assignment 5: Analysis and Project of FSMs, Digital Circuits and VHDL entities.