/Si5338-and-Si5351-Verilog

Si5338 and Si5351 Verilog

Primary LanguageVerilogMIT LicenseMIT

Unified IIC Initialization on both Si5338 and Si5351

This example initialize both programmable LVDS and Single-End Clock for FPGA (Verilog Based Xilinx Vivado 2020.2)

This example provide both a Windows EXE to convert the clock project from Si and converted into memory mem file.

The verilog design will read those files and initialize to the Si IC.

Report any bugs or ideas are highly-welcome. Enjoy =]