Pinned Repositories
ipxact2systemverilog
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
UART
OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verification component with error handling for parity, stop, and break errors.
ipxact2systemverilog
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
UART
OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verification component with error handling for parity, stop, and break errors.
Vitis_Libraries
Vitis Libraries
brucebenedictus's Repositories
brucebenedictus/ipxact2systemverilog
Translates IPXACT XML to synthesizable VHDL or SystemVerilog
brucebenedictus/UART
OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verification component with error handling for parity, stop, and break errors.