/alu-with-sequential-multiplier

ALU designed with Verilog HDL which includes sequential multiplier.

Primary LanguageVerilogMIT LicenseMIT

  • Project is implemented using Quartus II 13.1 (64-bit) Web Edition.
  • Archive file(qar), and verilog files are provided.
  • Test results, and design explanations are in the doc file.