A divide-by-two circuit quoted from Chapter 8 of the book "Low power CMOS circuits : technology logic design and CAD tools" by Christian Piguet
This divider circuit is just a positive-edge triggered D flip-flop of TSPC logic with Q_bar connected in loopback to D input.
initial D = 0
initial D = 1
TODO
- Improves the D flip flop to use split output latches design which has lesser mosfet and clock loadng.
