bysg

bysg's Stars

• tensil-ai/tensil

  Open source machine learning accelerators

  Language:Scala35329

• freecores/round_robin_arbiter

  round robin arbiter

  Language:Verilog6621

• riscv/riscv-isa-manual

  RISC-V Instruction Set Manual

  Language:TeX3.6k615

• apache/tvm-vta

  Open, Modular, Deep Learning Accelerator

  Language:Scala24671

• google-deepmind/alphatensor

  Language:Python2.7k232

• fengbintu/Neural-Networks-on-Silicon

  This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

  1.8k380

• aolofsson/oh

  Verilog library for ASIC and FPGA designers

  Language:Verilog1.2k284

• VerticalResearchGroup/miaow

  An open source GPU based off of the AMD Southern Islands ISA.

  Language:Verilog1k236

• alexforencich/verilog-ethernet

  Verilog Ethernet components for FPGA implementation

  Language:Verilog2.2k675

• basicmi/AI-Chip

  A list of ICs and IPs for AI, Machine Learning and Deep Learning.

  Language:PHP1.6k273

• LeiWang1999/FPGA

  帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

  3.8k655

• nvdla/hw

  RTL, Cmodel, and testbench for NVDLA

  Language:Verilog1.7k565

• riscv-mcu/e203_hbirdv2

  The Ultra-Low Power RISC-V Core

  Language:Verilog1.2k332

• jbush001/NyuziProcessor

  GPGPU microprocessor architecture

  Language:C2k351

• mntmn/amiga2000-gfxcard

  MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

  Language:Verilog99576

• cameronshinn/tiny-tpu

  Small-scale Tensor Processing Unit built on an FPGA

  Language:Verilog11718

• jofrfu/tinyTPU

  Implementation of a Tensor Processing Unit for embedded systems and the IoT.

  Language:VHDL38362

• UCSBarchlab/OpenTPU

  A open source reimplementation of Google's Tensor Processing Unit (TPU).

  Language:Python35168

• scalesim-project/scale-sim-v2

  Repository to host and maintain scale-sim-v2 code

  Language:Python21293

• ARM-software/SCALE-Sim

  Language:Python327151

• UT-LCA/tpu_like_design

  This repo contains a parameterizable TPU-like design (in Verilog) that will be overlayed onto an FPGA (probably PYNQ). We plan to add this design to VTR to serve as a benchmark for FPGA architecture exploration.

  Language:Verilog71

• karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2

  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator

  Language:SystemVerilog12127

• taoyilee/clacc

  Deep Learning Accelerator (Convolution Neural Networks)

  Language:Verilog16058

• wzc810049078/systolic-array-matrix-multiplier

  A systolic array matrix multiplier

  Language:Verilog225

• zhangzek/3x3_matrix_Systolic_Array_multiplier

  3×3脉动阵列乘法器

  Language:Verilog339

• cwfletcher/buffets

  Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.

  Language:Verilog6217

• dawsonjon/fpu

  synthesiseable ieee 754 floating point library in verilog

  Language:Verilog514142

• openhwgroup/cvfpu

  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

  Language:SystemVerilog418112

• HonkW93/automatic-verilog

  automatic-verilog based on vimscript

  Language:Vim Script23368

• fearyuan/automatic-for-verilog

  Language:Vim script1