/mips-ace

:spades:

Primary LanguageVerilogOtherNOASSERTION

MIPS - ACE

Implementation of a MIPS Processor developed during the course of Processor Architecture 2015 at UPC.

Features

  • Fully Pipelined
  • Hazard Control
  • MIPS friendly, high compatability
  • Mini OS
  • Exceptions
  • Benchmarks
  • Cache
  • Branch Prediction
  • Store Buffer
  • Virtual Memory
  • Variable Length Pipeline
  • Reorder Buffer / History File
  • Out-of-Order