CAD & Reliability Group
Works produced by the CAD & Reliability group of the Department of Control and Computer Engineering (DAUIN) of Politecnico di Torino
Italy
Pinned Repositories
.github
ase_riscv_gem5_sim
RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione
byron
An evolutionary source-code fuzzer
cv32e40p_tftlab
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
fenice
Customizable fault-simulation and gate-level editing library for sequential circuits
howto
A collection of howto guides
I99T
ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
pulpino_ri5cy_stls
Stuck-At Software Test Libraries for the pulpino-ri5cy SoC
r4ves
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
tflite-micro-x-heep
CAD & Reliability Group's Repositories
cad-polito-it/I99T
ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
cad-polito-it/ase_riscv_gem5_sim
RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione
cad-polito-it/byron
An evolutionary source-code fuzzer
cad-polito-it/fenice
Customizable fault-simulation and gate-level editing library for sequential circuits
cad-polito-it/pulpino_ri5cy_stls
Stuck-At Software Test Libraries for the pulpino-ri5cy SoC
cad-polito-it/cv32e40p_tftlab
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cad-polito-it/r4ves
RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.
cad-polito-it/.github
cad-polito-it/howto
A collection of howto guides
cad-polito-it/IPApproX
Set of IP management tools used within the context of the PULP project
cad-polito-it/pulpino_testing
SBST/FuSa environment for Pulpino - An open-source microcontroller system based on RISC-V
cad-polito-it/SFIadvancedmodels
cad-polito-it/tflite-micro-x-heep
cad-polito-it/x-heep-tflite-cfoshw24
cad-polito-it/x-heep-femu-tflite-sdk
X-HEEP-based FPGA EMUlation Platform (FEMU) Software Development Kit (SDK) with Tensorflow Lite for Microcontrollers support.