calvinee

32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

AMD_SummerSchool2022

第七组 队员：Chi kaisheng ren hao 课后题

An-Introduction-to-Statistical-Learning

This repository contains the exercises and its solution contained in the book An Introduction to Statistical Learning

antlr4

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

audio_noise_reduction_hardware_acceleration_system

基于PYNQ开发的人声音频降噪硬件加速系统，采用高通滤波器为主要算法，PYNQ-Z2开发板为上载硬件，采用PYNQ的软硬协同设计实现了实时的音频降噪功能，并且载入板卡后实现的效果，能够满足项目的开发需求。

BSV_Tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

Campus-WalkerCam

AMD-XilinxAdaptive Computing Challenge

darknet

YOLOv4 - Neural Networks for Object Detection (Windows and Linux version of Darknet )

FPGA_CNN_Number_Recognition

本项目最终实现了一个基于CNN算法的数字识别系统，通过摄像头输入图像，并通过VGA接口将摄像头原图和识别结果输出到显示屏上。

VERILOG-CNN-mnist-system

本项目使用 Vivado 和 SDK 工程软件上完成系统设计和生成相关部署文件，并在 ARM＋FPGA 完成项目部署，实现通过摄取图片并通过 ARM＋FPGA 综合部署和加速识别算法，并通过显示驱动，在显示屏上显示摄像头原图和识别结果。

calvinee/Design-and-Implementation-of-Face-Recognition-based-on-PYNQ

Face recognition, computer vision, deep learning, PYNQ, Movidius NCS

calvinee/Motion-Detection-System-Based-On-Background-Reconstruction

This work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to build a DMA based image data cache transmission system. On this basis, Verilog HDL was used to design the axi4-stream interface based IP core for image processing, so as to build a high real-time moving target detection system. In our design, we focus on the optimization of processing pipeline, improve the traditional frame difference method, and achieve the optimization goal of saving logical resources through the accumulation compression and reconstruction expansion of cached background frames.

calvinee/PYNQ-project

PYNQ, Neural network Language model, Overlay

calvinee/2019_SummerCamp

2019 SEU-Xilinx Summer School

calvinee/AutoRCCar

[hamuchiwa/AutoRCCar]项目的中文文档。每个代码文件都有同名markdwon文件来讲解。这是一个用 RC 小车、树莓派、Arduino和开源软件实现的小规模的自动驾驶项目。

calvinee/BP-Neural-Network-Matlab

BP Neural Network in Matlab.

calvinee/BYU_PYNQ_PR_Video_Pipeline

The Demo that was presented at FCCM.

calvinee/cnn-fpga-rtl

The CNN architecture elements implemented with RTL approach in VHDL.

calvinee/cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

calvinee/cosmoGAN

calvinee/CS_Gra-HITsz

哈尔滨工业大学（深圳）计算机科学与技术研究生课程

calvinee/DAC2018-TGIIF

The 1st place winner's source codes for DAC 2018 System Design Contest, FPGA Track

calvinee/dashee87.github.io

:triangular_ruler: A flexible two-column Jekyll theme. Perfect for personal sites, blogs, and portfolios hosted on GitHub or your own server.

calvinee/Deep-Learning-Hardware-Accelerator

Paper Collection of Deep Learning Hardware Accelerator

calvinee/Deep-Neural-Network-Hardware-Accelerator-1

My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket

calvinee/Digital-Design-with-Verilog

Projects done for Advanced Digital Design with Verilog. Examples include code for applications like Sobel Edge Detection and DTMF generation.

calvinee/FPGAEyeTracker

FPGA EyeTracker

calvinee/HIT-Courses

哈尔滨工业大学课程资料分享

calvinee/hwac_object_tracker

FPGA accelerated TinyYOLO v2 object detection neural network

calvinee/labview2018-tutorial

this repository tells how to use LabVIEW based on labview2018.

calvinee/LabView_Stm32

labview编写stm32

calvinee/Labview_study

学习Labview，包含学习过程中的笔记资料，案列教程等。

calvinee/LinearAlgebra

线性代数、矩阵理论笔记整理

calvinee/Machine_Learning_bookshelf

机器学习深度学习相关书籍、课件、代码的仓库。 Machine learning is the warehouse of books, courseware and codes.

calvinee/msra-walking-robot

Example files for MATLAB and Simulink Robotics Arena walking robot videos.

calvinee/PyTorch-YOLOv3

Minimal PyTorch implementation of YOLOv3

calvinee/StringArt

Generate art from string

calvinee/USTC-CS-Courses-Resource

:heart:**科学技术大学计算机学院课程资源(https://mbinary.xyz/ustc-cs/)

calvinee/verilog-style

A coding style reference for verilog

calvinee/xduthesis

XeLaTeX template for writing thesis aiming to apply degrees from Xidian University.