Pinned Repositories
atomicc
Generate Verilog from Atomicc IR files (which are generated from llvm-translate)
atomicc-examples
bsvtokami
Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.
connectal
Connectal is a framework for software-driven hardware development.
fpgajtag
A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
fpgamake
Generates Makefiles to synthesize, place, and route verilog using Vivado
libwebsockets
open-src-cvc
Mirror of tachyon-da cvc Verilog simulator
xbsv
connectal (formerly called xbsv) contains a utility to generate bit files for Xilinx Zynq devices from BSV programs.
zynq-boot
Scripts to create a boot.bin file for linux on Xilinx Zync
cambridgehackers's Repositories
cambridgehackers/connectal
Connectal is a framework for software-driven hardware development.
cambridgehackers/fpgamake
Generates Makefiles to synthesize, place, and route verilog using Vivado
cambridgehackers/open-src-cvc
Mirror of tachyon-da cvc Verilog simulator
cambridgehackers/fpgajtag
A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
cambridgehackers/bsvtokami
Translates Bluespec SystemVerilog to Kami for use with the coq proof assistant.
cambridgehackers/xbsv
connectal (formerly called xbsv) contains a utility to generate bit files for Xilinx Zynq devices from BSV programs.
cambridgehackers/atomicc
Generate Verilog from Atomicc IR files (which are generated from llvm-translate)
cambridgehackers/buildcache
Memoizes execution of build commands
cambridgehackers/atomicc-examples
cambridgehackers/linux-xlnx
The official Linux kernel from Xilinx
cambridgehackers/bsc-contrib
A place to share libraries and utilities that don't belong in the core bsc repo
cambridgehackers/clang
Mirror of official clang git repository located at http://llvm.org/git/clang. Updated every five minutes.
cambridgehackers/cudd
CUDD: CU Decision Diagram package - unofficial git mirror of http://vlsi.colorado.edu/~fabio/
cambridgehackers/llvm
Branch of llvm repository. Use branch release_34atomicc1
cambridgehackers/llvm-translate
llvm runtime interpreter/translator
cambridgehackers/openocd
packaging branch of openocd
cambridgehackers/PYNQ
Python Productivity for ZYNQ with Python board level designs
cambridgehackers/verilog-rewrite
A tool to rewrite xilinx synthesized netlists back into non-LUT form (to manually verify elaboration)
cambridgehackers/bsc
Bluespec Compiler (BSC)
cambridgehackers/consolable
cambridgehackers/cplusplus_draft
C++ standards drafts
cambridgehackers/doc
Repository for publishing non-jekyll documentation
cambridgehackers/dumpNet
cambridgehackers/NuSMV
Mirror of NuSMV 2.6.0 from http://nusmv.fbk.eu
cambridgehackers/pciescan
cambridgehackers/tlaplus
TLC is an explicit state model checker for specifications written in TLA+. The TLA+Toolbox is an IDE for TLA+.
cambridgehackers/verilator
Verilator open-source SystemVerilog simulator and lint system
cambridgehackers/verilator.jeremybennett
A fork of the main Verilator project for development work.
cambridgehackers/verilog-vcd-parser
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
cambridgehackers/XilinxUnisimLibrary