Vitis RTL samples

This repository holds different Vitis projects, which implement RTL kernels written in Verilog. Some are generated using the RTL Kernel Wizard in Xilinx Vivado, while others are a mix of generated files and hand-written RTL files.

Prerequisites

CMake >= 3.12.4
Xilinx Vitis 2020.1
Xilinx Runtime Library (XRT)
A Xilinx platform, such as the Xilinx Alveo U250 platform

Building/running a project

First, all of the environment variables for Xilinx Vivado need to be set. An example shell file with the default variables can be sourced or added to rc file (e.g. ~/.bashrc):

source source.sh

To generate all of the build scripts in a folder called build/:

cmake -Bbuild -H.

To build all of the projects:

cmake --build build

To build a single project, here byteswap is used as an example:

cmake --build build --target build_byteswap

To run all of the projects:

cmake --build build --target run

To run a single project, here byteswap is used as an example:

cmake --build build --target run_byteswap

Project file structure

Files encapsulated in [] are optional files and folders. Filenames with * indicates the glob pattern for source files. The filenames such as rtl_kernel_0 and hls_kernel_0 are purely suggestions.

project/
|-- CMakeLists.txt          # cmake configuration
`-- src
    |-- [configs]           # optional folder for v++ configs
    |   |-- [build.ini]     # optional v++ config for build HLS kernels
    |   |-- [link.ini]      # optional v++ config for linking .xo kernels
    |   `-- [package.ini]   # optional v++ config for packaging .xclbin binary
    |-- [hdl]
    |   `-- rtl_kernel_0
    |   |   |-- kernel.json # kernel configuration for generating scripts
    |   |   |-- *.v
    |   |   `-- *.sv
    |   `-- rtl_kernel_1
    |       |-- kernel.json
    |       |-- *.v
    |       `-- *.sv
    |-- [hls]
    |   |-- hls_kernel_0.cpp
    |   `-- hls_kernel_1.cpp
    `-- host.cpp

Projects

Byteswap - Swaps the order of bytes for each 32 bit input, so the least significant byte becomes the most significant byte.
Vector add - Sums the two input vectors. It is a modified version of the Xilinx sample.
Vector add floating point - Same as Vector add, but uses the Xilinx Floating Point IP for the addition.
Vector add floating point hls - Multi kernel Vector add, with HLS for memory management and with RTL as compute kernel.
Vector add floating point hls pure - Multi kernel Vector add, written purely in HLS.

Utilities

CMakeLists - cmake file containing all the rules and commands for building the projects.
rtl/ - RTL library with implementations of utility cores.
- axi_counter - Counter, which is used by the AXI cores.
- axi_read_master - Multi channel AXI read master.
- axi_write_master - Multi channel AXI write master.
templates/ - Python scripts for generating TCL scripts and RTL files.
- control - Python script for generating a Verilog controller for Vitis.
- package - Python script for generating a TCL script for packaging an RTL kernel into an .xo file.
- synth - Python script for generating a TCL script for elaborating and synthesizing RTL kernels for finding errors, such as syntax errors.
utils.mk (deprecated) - Makefile for building all of the projects.