Issues
- 0
docs failing after merge
#213 opened by jkocz - 8
- 2
Guide to add new supported platform
#210 opened by TuringTW - 2
RFDC block stops working if .slx file is renamed
#199 opened by gallicchio - 3
Address/size inconsicencites for microblaze
#184 opened by kiranshila - 4
update_casper_blocks doesn't seem to be permanent
#202 opened by kiranshila - 1
RFSoC 2x2 Backend compile issue - missing tile228?
#204 opened by harshadms - 2
- 7
Test models out of date
#200 opened by jkocz - 4
JAM indexing errors prevents compilation
#185 opened by kiranshila - 3
RFDC needs to be on top-level of Simulink diagram
#194 opened by jack-h - 2
RFSoC: No recursive cloning in tutorial instructions
#193 opened by jwkunz - 1
Issue and/or Feature Request: Automatic updating of IP
#192 opened by jwkunz - 1
Compatiability Matrix in Documentation
#190 opened by jwkunz - 0
SNAP Microblaze support is currently broken
#181 opened by kiranshila - 9
- 3
pfb_fir_real no longer accepts parameters
#176 opened by kiranshila - 1
Some ADC yellow blocks have non-intuitive interfaces and/or no/limited simulation behaviour
#166 opened by amartens - 0
- 1
A repository installation issue with ROACH2
#151 opened by wzwzhao - 0
Installation error of Xilinx USB Cable Driver
#156 opened by yangyt96 - 0
- 5
- 0
AXI BRAM fixed latency
#145 opened - 1
setup.py error
#144 opened by indrajitbarve - 2
exec_flow partial compiles
#141 opened - 5
Default yaml loader issue
#139 opened by cain986 - 3
CASPER Actions: Ethernet Memory Map Harmonization
#28 opened by jack-h - 2
SNAP TX_DISABLE wrong polarity
#30 opened by jack-h - 5
Version Info on the front page of readthedocs
#86 opened by jack-h - 3
- 1
dec_fir block complex output issue
#118 opened by aragorn2101 - 1
make matlab return values more useful
#96 opened by jack-h - 0
Shared BRAM initial values
#5 opened by amartens - 2
To Software register bit fields
#46 opened by wnew - 2
FFT mask error -- shift schedule
#84 opened by jack-h - 1
Neaten XML2VHDL inclusion
#88 opened - 2
- 1
onegbe merge messed up
#91 opened by jack-h - 2
Version checking?
#13 opened by cs150bf - 2
\n in register names break jasper.per
#18 opened by gshippee - 4
Software register initial value
#4 opened by amartens - 2
No platform names in gpio blocks
#26 opened by jack-h - 1
JASPER Shared BRAM Yellow Block Simulation
#47 opened by jkocz - 1
CASPER Actions: FPGA hardware matrix
#27 opened by jack-h - 4
Outstanding ROACH2 yellow blocks
#2 opened by amartens - 1
- 1
Ethernet multicast support
#3 opened by amartens - 1
Shared BRAM performance
#9 opened by amartens - 4
FFT copy/paste problem
#6 opened by amartens