cfriedt/zephyr-on-litex-vexriscv

Zephyr-on-litex-vexriscv

Zephyr on LiteX VexRiscv is a LiteX SoC builder for the litex_vexriscv platform in Zephyr. Currently it supports Digilent Arty A7-35T Development Board.

Prerequisites

First, you have to install the F4PGA toolchain. It can be done by following instructions in this tutorial.

Then, clone and enter the Zephyr-on-litex-vexriscv repository:

git clone https://github.com/litex-hub/zephyr-on-litex-vexriscv.git && cd zephyr-on-litex-vexriscv

Get all required submodules and packages, and run the install script:

git submodule update --init --recursive
apt-get install build-essential bzip2 python3 python3-dev python3-pip
./install.sh

Build

Build the bitstream by following these steps:

• Add LiteX to path:

source ./init

• Prepare F4PGA environment:

export INSTALL_DIR="path/to/f4pga"
FPGA_FAM="xc7"
export PATH="$INSTALL_DIR/$FPGA_FAM/install/bin:$PATH";
source "$INSTALL_DIR/$FPGA_FAM/conda/etc/profile.d/conda.sh"
conda activate $FPGA_FAM

• Finally build the bitstream:

./make.py --board=arty --build

Build options

Option	Help
--toolchain	FPGA toolchain
--board	FPGA board
--build	build bitstream
--variant	FPGA board variant
--load	load bitstream
--with-ethernet	Enable ethernet
--with_i2s	Enable i2s
--sys-clk-freq	System clock frequency
--with_spi	Enable SPI
--with_i2c	Enable i2c
--with_pwm	Enable PWM
--spi-data-width	SPI data width
--spi-clk-freq	SPI clock frequency
--with_mmcm	Enable MMCM
--local-ip	local IP address
--remote-ip	remote IP address

Load bitstream

Connect your board using the serial port and load the bitstream:

source ./init
./make.py --board=arty --load