ch1bug

ch1bug's Stars

• AgibotTech/agibot_x1_train

  The reinforcement learning training code for AgiBot X1.

  Language:Python988296

• AgibotTech/agibot_x1_infer

  The inference module for AgiBot X1.

  Language:C++1k321

• AgibotTech/agibot_x1_hardware

  The hardware design for AgiBot X1.

  550174

• jankae/LibreVNA

  100kHz to 6GHz 2 port USB based VNA

  Language:C++1.1k209

• jakkra/ZSWatch

  ZSWatch - the Open Source Zephyr™ based Smartwatch, including both HW and FW.

  Language:C2.3k204

• chipsalliance/chisel

  Chisel: A Modern Hardware Design Language

  Language:Scala4k594

• Digital-EDA/Digital-IDE

  All in one vscode plugin for HDL development

  Language:Verilog39711

• d2l-ai/d2l-en

  Interactive deep learning book with multi-framework code, math, and discussions. Adopted at 500 universities from 70 countries including Stanford, MIT, Harvard, and Cambridge.

  Language:Python23.7k4.3k

• d2l-ai/d2l-zh

  《动手学深度学习》：面向中文读者、能运行、可讨论。中英文版被70多个国家的500多所大学用于教学。

  Language:Python63.1k11k

• ridecore/ridecore

  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

  Language:Verilog32263

• krahets/hello-algo

  《Hello 算法》：动画图解、一键运行的数据结构与算法教程。支持 Python, Java, C++, C, C#, JS, Go, Swift, Rust, Ruby, Kotlin, TS, Dart 代码。简体版和繁体版同步更新，English version ongoing

  Language:Java97.8k12.4k

• rtlabs-com/i-link

  IO-Link master stack for embedded devices

  Language:C5431

• unref-ptr/lwIOLink

  Language:C++6012

• ZengjfOS/Modbus_TCP

  目标是分析Modbus TCP协议，对B-L475E-IOT01A STM32源代码进行了分析，理解其MQTT、Modbus协议通信工作原理。

  1110

• WeitaoZhu/Communications_System

  通信系统类书籍(无线通信，数字通信，信号系统，通信原理等)

  328

• ciaa/Hardware

  Hardware de la CIAA

  Language:HTML167163

• sin-x/FPGA

  数字IC相关资料

  959284

• riscv-admin/exchange

  RISC-V Exchange is a dedicated repository designed to facilitate comprehensive and structured discussions within the RISC-V community.

  6

• suisuisi/FPGA_Library

  Vivado诸多IP，包括图像处理等

  Language:VHDL16042

• mortbopet/Ripes

  A graphical processor simulator and assembly editor for the RISC-V ISA

  Language:C++2.6k275

• lnis-uofu/OpenFPGA

  An Open-source FPGA IP Generator

  Language:Verilog827162

• LeiWang1999/FPGA

  帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

  4k668

• XUANTIE-RV/wujian100_open

  IC design and development should be faster，simpler and more reliable

  Language:Verilog1.9k572

• riscv-mcu/e203_hbirdv2

  The Ultra-Low Power RISC-V Core

  Language:Verilog1.3k341

• microdynamics-cpu/tree-core-ide

  :deciduous_tree: The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

  Language:JavaScript9915

• OpenXiangShan/XiangShan

  Open-source high-performance RISC-V processor

  Language:Scala4.8k654

• viduraakalanka/HDL-Bits-Solutions

  This is a repository containing solutions to the problem statements given in HDL Bits website.

  Language:Verilog32689

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.6k378

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.1k285

• huangpengfen/GD32F103_FreeRTOS_GCC

  Language:C81