Pinned Repositories
awesome-machine-learning
A curated list of awesome Machine Learning frameworks, libraries and software.
awesome-rnn
Recurrent Neural Network - A curated list of resources dedicated to RNN
CRNN_Tensorflow
Convolutional Recurrent Neural Networks(CRNN) for Scene Text Recognition
ctc-ocr-tensorflow
continuously mnist with rnn ctc
CTCWordBeamSearch
Connectionist Temporal Classification (CTC) decoder with dictionary and language model for TensorFlow.
Deep-Learning-for-Tracking-and-Detection
Collection of papers and other resources for object tracking and detection using deep learning
lstm-ctc-ocr
using rnn (lstm or gru) and ctc to convert line image into text, based on torch7 and warp-ctc
peta_linux_commnads
petalinux commands
python_networking
basic python networking
scikit-image
Image Processing SciKit (Toolbox for SciPy)
chaitusvk's Repositories
chaitusvk/acwj
A Compiler Writing Journey
chaitusvk/astra-sim
ASTRA-sim2.0: Modeling Hierarchical Networks and Disaggregated Systems for Large-model Training at Scale
chaitusvk/astra_sim_complete
complete_astrasim
chaitusvk/Awesome-GPU
Awesome resources for GPUs
chaitusvk/Butterfly_Acc
The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design"
chaitusvk/c-compiler
A compiler that accepts any valid program written in C. It is made using Lex and Yacc. Returns a symbol table, parse tree, annotated syntax tree and intermediate code.
chaitusvk/cs6120
advanced compilers
chaitusvk/CuAssembler
An unofficial cuda assembler, for all generations of SASS, hopefully ：）
chaitusvk/HIFIVE1-VP
A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS
chaitusvk/llm_dims
Open LLM dimensions
chaitusvk/marss-riscv
TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
chaitusvk/ONNXim
ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
chaitusvk/or1kiss
An OpenRISC 1000 Instruction Set Simulator
chaitusvk/or1kmvp
An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
chaitusvk/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
chaitusvk/PIMSim
PIMSim is a Process-In-Memory Simulator with the compatibility of GEM5 full-system simulation.
chaitusvk/PIMSimulator
Processing-In-Memory (PIM) Simulator
chaitusvk/RISC-V-Pipeline
32-bit 5-stage pipelined RISC-V processor in SystemVerilog
chaitusvk/RISC-V-TLM
RISC-V SystemC-TLM simulator
chaitusvk/riscv
RISC-V CPU Core (RV32IM)
chaitusvk/riscv-simple-sv
A simple RISC V core for teaching
chaitusvk/riscv-vp
RISC-V Virtual Prototype
chaitusvk/rsd
RSD: RISC-V Out-of-Order Superscalar Processor
chaitusvk/rv32emu
RISC-V RV32I[MACF] emulator with ELF support
chaitusvk/sparcity_transformers
chaitusvk/system_verilog_codes
system verilog codes
chaitusvk/SystemC-Components
A SystemC productivity library: https://minres.github.io/SystemC-Components/
chaitusvk/telugu_ocr_multi_line
telugu ocr CRNN mult line
chaitusvk/tlm2-interfaces
contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
chaitusvk/vcml
A modeling library with virtual components for SystemC and TLM simulators