chandanpalai
Hi, I am passionate about hardware design and coding. I'm self trained in many languages and have had professional training in VHDL & Verilog
Pune
Pinned Repositories
astroFPGA
18-545 Astroteam computer vision project repository
bitgpu
BitGPU is a GPU approach to solve the bitwidth optimization problem in FPGA datapaths.
CNC
CNC Proyect over FPGA
CPUonFPGA
It's a basic computer designed using VERILOG on XILINX FPGA architecture.
fpga-cf
FPGA Communication Framework
FPGA-Dev
This contains various projects involving FPGAs that I have completed or am still in the process of developing
FPGA-SoC-Linux
FPGA+SoC+Linux Boot Images (Xilinx:Zynq-Zybo Altera:de0-nano-soc)
fpga_dac
Project which creates an analogic sine signal from an architecture that involves FPGA. It were used a DDS core to generate the sine and SPI communication to control DAC conversor (AD5791 Analog Devices). To choose the sine frequency and the update frequency of a new data we developed a cpp application. The "documentation" folder has more details of the project, including datasheets, state machine and block diagram.
FpgaMicrotubule
HPC Implementation of dynamic microtubules calculations on CPU, GPU and FPGA Platforms
SystemVerilog-Assertions
Examples of assertions used in SystemVerilog. Made for udemy course by M. Ramdas
chandanpalai's Repositories
chandanpalai/SystemVerilog-Assertions
Examples of assertions used in SystemVerilog. Made for udemy course by M. Ramdas
chandanpalai/bitgpu
BitGPU is a GPU approach to solve the bitwidth optimization problem in FPGA datapaths.
chandanpalai/CNC
CNC Proyect over FPGA
chandanpalai/FPGA-SoC-Linux
FPGA+SoC+Linux Boot Images (Xilinx:Zynq-Zybo Altera:de0-nano-soc)
chandanpalai/hailfire-fpga
HDL for the FPGA in the Hailfire robot, using MyHDL and Quartus
chandanpalai/OpenCL
This project contains code developed by a research team at University of Colorado,Boulder and Embry Riddle Aeronautical University to explore FPGA and GP-GPU co-processor power efficiency for continous transform 3D mapping and sensor fusion. Please use at your own risk. We are sharing so that other researchers and developers can recreate our results and make suggestions to improve and extend the benchmarks over time. The results we obtained were documented in the SPIE Sensor and Technologies paper: S. Siewert, V. Angoth, R. Krishnamurthy, K. Mani, K. Mock, S. B. Singh, S. Srivistava, C. Wagner, R. Claus, M. Demi Vis, “Software Defined Multi-Spectral Imaging for Arctic Sensor Networks”, SPIE Algorithms and Technologies for Multipectral, Hyperspectral, and Ultraspectral Imagery XXII, Baltimore, Maryland, April 2016. This repository includes FPGA codes
chandanpalai/RedPitaya
Red Pitaya Ecosystem and Applications
chandanpalai/riscv_vhdl
VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".
chandanpalai/UVM-sample-codes
This contains UVM basic example codes
chandanpalai/aes-fpga
AES implementation on FPGA
chandanpalai/arduino
FPGArduino
chandanpalai/Brew
Quartus Verilog Brew to test with float fix and multiplication
chandanpalai/fpga-drive-aximm-pcie
Example design for FPGA Drive using the AXI Memory Mapped to PCI Express Bridge IP
chandanpalai/freedom-e-sdk
Open Source Software for Developing on the Freedom E Platform
chandanpalai/linuxcnc
LinuxCNC controls CNC machines. It can drive milling machines, lathes, 3d printers, laser cutters, plasma cutters, robot arms, hexapods, and more.
chandanpalai/myhdl
The MyHDL development repository
chandanpalai/ogr2osm
UVM's Rewrite of ogr2osm
chandanpalai/pcie5_phy
PCIE 5.0 Graduation project (Verification Team) under supervision of Mentor Graphics
chandanpalai/Practical-UVM-Step-By-Step
This is the main repository for all the examples for the book Practical UVM
chandanpalai/robinsun-fpga
Code for the FPGA of the Robinsun robot.
chandanpalai/samplecode
This repository contains sample code for different Numato Lab products
chandanpalai/SystemVerilog-Basics
Contains basic sample codes for SystemVerilog.
chandanpalai/SystemVerilogAssertions
Examples and reference for System Verilog Assertions
chandanpalai/SystemVerilogReference
training labs and examples
chandanpalai/test1
trial
chandanpalai/uvm-tutorial-for-candy-lovers
Source code repo for UVM Tutorial for Candy Lovers
chandanpalai/uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
chandanpalai/Verilog-sample-codes
Repository for basic and advanced Verilog sample codes created for CDAC VLSI 2016 course
chandanpalai/verilog_systemverilog.vim
Verilog/SystemVerilog Syntax and Omni-completion
chandanpalai/VHDL-example-codes
VHDL lab codes created for CDAC VLSI 2016 course