Papers & Codes

This is a collection of Design Space Exploration (DSE) papers and corresponding open-source codes (if exist) for designing Deep Learning Accelerator (DLA).

General

Depth-first/Layer-fusion

  • (2021 IEEE Access) ConvFusion: A Model for Layer Fusion in Convolutional Neural Networks
  • (2021 IEEE J Em Sel Top C) Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing
  • (2022 Arxiv) DNNFuser: Transformer as a Generalized Mapper for Fusion in DNN Accelerators
  • (2022 Electronics) HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures
  • (2023 ASPLOS) FLAT: An Optimized Dataflow for Mitigating Attention Bottlenecks
  • (2023 HPCA) DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling

Others