/ReWire

Experimental compiler for a subset of Haskell to VHDL

Primary LanguageVHDLOtherNOASSERTION

ReWire

Build Status

ReWire is an experimental compiler for a subset of Haskell to VHDL, suitable for synthesis and implementation on FPGAs. ReWire enables a semantics-directed style of synchronous hardware development, based on reactive resumption monads. See the online documentation for more information.