Pinned Repositories
-stm32F769_emwin-
基于stm32F769_emwin的数字可编程直流稳压电源
HLS_Legup
IWR6843-Read-Data-Python-MMWAVE-SDK
Read IWR6843ISK sensor serial data using Python
IWR6843_TLVS
Obtain detected points from IWR6843aop.
IWR6843AOP-get-heatmap
Use IWR6843AOP to collect radar data after one FFT and process it into horizontal or vertical heat map
phasesimulator
This repository is meant to create an alternative to RITSAR in cpp rather than Python to optimize in speed.
pynq_new_cases
outree cases of pynq
pynq_onlyZ2
modify pynq reposity only remain pynqz2
Pythonic
Graphical Python programming for trading and automation
RITSAR
Synthetic Aperture Radar (SAR) Image Processing Toolbox for Python
chenguoping76's Repositories
chenguoping76/-stm32F769_emwin-
基于stm32F769_emwin的数字可编程直流稳压电源
chenguoping76/HLS_Legup
chenguoping76/IWR6843-Read-Data-Python-MMWAVE-SDK
Read IWR6843ISK sensor serial data using Python
chenguoping76/IWR6843_TLVS
Obtain detected points from IWR6843aop.
chenguoping76/IWR6843AOP-get-heatmap
Use IWR6843AOP to collect radar data after one FFT and process it into horizontal or vertical heat map
chenguoping76/phasesimulator
This repository is meant to create an alternative to RITSAR in cpp rather than Python to optimize in speed.
chenguoping76/pynq_new_cases
outree cases of pynq
chenguoping76/pynq_onlyZ2
modify pynq reposity only remain pynqz2
chenguoping76/Pythonic
Graphical Python programming for trading and automation
chenguoping76/RITSAR
Synthetic Aperture Radar (SAR) Image Processing Toolbox for Python
chenguoping76/SAR-Synthetic-Aperture-Radar
合成孔径雷达 相关。研究生期间学习 SAR/InSAR/PolSAR 相关的代码和总结，毕业后已经离开这个领域了。分享出来，仅此纪念。1）SAR: 成像算法，RD，CS，Radarsat-1数据成像处理。2）InSAR: 人造场景原始回波仿真、成像及干涉处理。包括平地场景和圆锥形场景。3）PolSAR: 极化定标算法，Whitt, PARC, Quegan, Ainsworth。详见 readme.md
chenguoping76/video-sdk-gstreamer
chenguoping76/Vitis-Tutorials
Vitis In-Depth Tutorials
chenguoping76/write-pythonic-code-demos
Write Pythonic Code Like a Seasoned Developer video course demo materials.
chenguoping76/Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.