Pinned Repositories
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
openpiton
The OpenPiton Platform
opensbi
RISC-V Open Source Supervisor Binary Interface
riscv-tools
RISC-V Tools (ISA Simulator and Tests)
usb3_pipe
USB3 PIPE interface for Xilinx 7-Series
verilog-ethernet
Verilog Ethernet components for FPGA implementation
cheungivan's Repositories
cheungivan/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
cheungivan/openpiton
The OpenPiton Platform
cheungivan/opensbi
RISC-V Open Source Supervisor Binary Interface
cheungivan/riscv-tools
RISC-V Tools (ISA Simulator and Tests)
cheungivan/usb3_pipe
USB3 PIPE interface for Xilinx 7-Series
cheungivan/verilog-ethernet
Verilog Ethernet components for FPGA implementation