Doubt
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Hello,
Sorry for posting my question here. I heard you were the expert in the topic which I am currently doing.
I am trying to establish openocd connection to the murax Soc (VexRiscv) core inside my arty A7 Fpga.
Can you please help me with the steps?
Until now I have used bscan to jtag IP and debug bridge IP in Xilinx, where I was able to see the ID of the murax, but I am able to establish openocd connection in ubuntu. please help me in this.
Thank You
Haha, I’m not the expert, just know a little about Chisel and RocketChip.
AFAIK, VexRiscv is not a chisel project, i believe it belongs to SpinalHDL, which was a fork from Chisel, and I have no knowledge to it.
as for BSCAN, I had a implementation in fpga-shells, which was ready tested with Arth A7, but I think currently it only support rocket core.
You can contact me directly with email, we can discuss your project with email. :)