Issue when using vc707 in chipyard
Closed this issue · 4 comments
Hi, I'm currently using vc707 with the chipyard project. During compilation, vivado emits an error and quits. The terminal shows something like this
****** Vivado v2021.2 (64-bit)
**** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
**** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source /home/loriland/Documents/chipyard/fpga/fpga-shells/xilinx/common/tcl/vivado.tcl
# set scriptdir [file dirname [info script]]
# source [file join $scriptdir "prologue.tcl"]
## set ip_vivado_tcls {}
## while {[llength $argv]} {
## set argv [lassign $argv[set argv {}] flag]
## switch -glob $flag {
## -top-module {
## set argv [lassign $argv[set argv {}] top]
## }
## -F {
## # This should be a simple file format with one filepath per line
## set argv [lassign $argv[set argv {}] vsrc_manifest]
## }
## -board {
## set argv [lassign $argv[set argv {}] board]
## }
## -ip-vivado-tcls {
## set argv [lassign $argv[set argv {}] ip_vivado_tcls]
## }
## -pre-impl-debug-tcl {
## set argv [lassign $argv[set argv {}] pre_impl_debug_tcl]
## }
## -post-impl-debug-tcl {
## set argv [lassign $argv[set argv {}] post_impl_debug_tcl]
## }
## -env-var-srcs {
## set argv [lassign $argv[set argv {}] env_var_srcs]
## }
## default {
## return -code error [list {unknown option} $flag]
## }
## }
## }
## if {![info exists top]} {
## return -code error [list {--top-module option is required}]
## }
## if {![info exists vsrc_manifest]} {
## return -code error [list {-F option is required}]
## }
## if {![info exists board]} {
## return -code error [list {--board option is required}]
## }
## set commondir [file dirname $scriptdir]
## set boarddir [file join [file dirname $commondir] $board]
## source [file join $boarddir tcl board.tcl]
### set name {vc707}
### set part_fpga {xc7vx485tffg1761-2}
### set part_board {xilinx.com:vc707:part0:1.3}
## set constraintsdir [file join $boarddir constraints]
## set srcdir [file join $commondir vsrc]
## set wrkdir [file join [pwd] obj]
## set ipdir [file join $wrkdir ip]
## create_project -part $part_fpga -force $top
create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2506.340 ; gain = 0.000 ; free physical = 20050 ; fre
e virtual = 60480
## set_param messaging.defaultLimit 1000000
## set_property -dict [list \
## BOARD_PART $part_board \
## TARGET_LANGUAGE {Verilog} \
## DEFAULT_LIB {xil_defaultlib} \
## IP_REPO_PATHS $ipdir \
## ] [current_project]
ERROR: [Board 49-71] The board_part definition was not found for xilinx.com:vc707:part0:1.3. The project's board_part property was not se
t, but the project's part property was set to xc7vx485tffg1761-2. Valid board_part values can be retrieved with the 'get_board_parts' Tcl
command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.
INFO: [Common 17-17] undo 'set_property'
while executing
"rdi::add_properties -dict {BOARD_PART xilinx.com:vc707:part0:1.3 TARGET_LANGUAGE Verilog DEFAULT_LIB xil_defaultlib IP_REPO_PATHS /home/
loriland/Docum..."
invoked from within
"set_property -dict [list \
BOARD_PART $part_board \
TARGET_LANGUAGE {Verilog} \
DEFAULT_LIB {xil_defaultlib} \
IP_REPO_PATHS $ipdir \
] [current_..."
(file "/home/loriland/Documents/chipyard/fpga/fpga-shells/xilinx/common/tcl/prologue.tcl" line 78)
while executing
"source [file join $scriptdir "prologue.tcl"]"
(file "/home/loriland/Documents/chipyard/fpga/fpga-shells/xilinx/common/tcl/vivado.tcl" line 7)
INFO: [Common 17-206] Exiting Vivado at Mon Nov 14 21:01:25 2022...
make: *** [Makefile:129: /home/loriland/Documents/chipyard/fpga/generated-src/chipyard.fpga.vc707.VC707FPGATestHarness.RocketVC707Config/
obj/VC707FPGATestHarness.bit] Error 1
Went to xilinx/vc707/tcl/board.tcl to check, found that if I modify the part_board value from xilinx.com:vc707:part0:1.3 to xilinx.com:vc707:part0:1.4, program runs correctly.
Not sure if this is a bug, but probably need a fix
Verified on running instances of Vivado. Running get_board_parts in tcl mode returned
In 2021.2:
xilinx.com:k26c:part0:1.2 xilinx.com:k26c:part0:1.3 xilinx.com:k26i:part0:1.2 xilinx.com:k26i:part0:1.3 xilinx.com:kv260_som:part0:1.2 xilinx.com:vc707:part0:1.4 xilinx.com:vc709:part0:1.8
In 2022.2:
xilinx.com:k26c:part0:1.2 xilinx.com:k26c:part0:1.3 xilinx.com:k26c:part0:1.4 xilinx.com:k26i:part0:1.2 xilinx.com:k26i:part0:1.3 xilinx.com:k26i:part0:1.4 xilinx.com:kr260_som:part0:1.0 xilinx.com:kr260_som:part0:1.1 xilinx.com:kv260_som:part0:1.2 xilinx.com:kv260_som:part0:1.3 xilinx.com:kv260_som:part0:1.4 xilinx.com:vc707:part0:1.4 xilinx.com:vc709:part0:1.8 xilinx.com:vcu118:part0:2.0 xilinx.com:vcu118:part0:2.3 xilinx.com:vcu118:part0:2.4 xilinx.com:vcu1525:part0:1.3
Because Xilinx has removed support for board_part=xilinx.com:vc707:part0:1.3 for over two years, this must be fixed to avoid breakage.
resolved by #7
Hello, @Lorilandly. My team intends to buy a vcu118 evaluation board for evaluate the prototype based on chipyard. But seems that there are Rev1 and Rev2 versions of vcu118. I don't know which one We should choose so that the official chipyard design will work. I am new to FPGA. I want to know if the REV1 and REV2 are the same in terms of chipyard mapping, thanks!
@jerryhethatday I’m really not an expert and have not used vcu118 before. I hope this document from xilinx can help.