cigarliang's Stars
renyunkang/yuque-exporter
A tool for exporting Yuque documents as markdown.
linyiLYi/street-fighter-ai
This is an AI agent for Street Fighter II Champion Edition.
wudayemen/gen_apb_file
riscv-mcu/e203_hbirdv2
The Ultra-Low Power RISC-V Core
adki/AMBA_AXI_AHB_APB
AMBA bus lecture material
hpcn-uam/Limago
Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
freecores/mac_layer_switch
100 MB/s Ethernet MAC Layer Switch
freecores/dma_axi
AXI DMA 32 / 64 bits
Xilinx/dma_ip_drivers
Xilinx QDMA IP Drivers
XUANTIE-RV/openc910
OpenXuantie - OpenC910 Core
riscvarchive/riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
KastnerRG/riffa
The RIFFA development repository
analogdevicesinc/hdl
HDL libraries and projects
LeiWang1999/FPGA
帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目
magro732/OpenRIO
Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
defparam/PCI2Nano-RTL
An open source FPGA PCI core & 8250-Compatible PCI UART core
defparam/BAR-Tender
An FPGA I/O Device which services physical memory reads/writes via UMDF2 driver
GOOD-Stuff/srio_test
Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)
freecores/xge_mac
Ethernet 10GE MAC
alexforencich/myhdl
The MyHDL development repository
alexforencich/corundum
Open source FPGA-based NIC and platform for in-network compute
alexforencich/verilog-i2c
Verilog I2C interface for FPGA implementation
alexforencich/verilog-wishbone
Verilog wishbone components
alexforencich/verilog-ethernet
Verilog Ethernet components for FPGA implementation
alexforencich/cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
alexforencich/verilog-axi
Verilog AXI components for FPGA implementation
alexforencich/verilog-pcie
Verilog PCI express components
alexforencich/verilog-uart
Verilog UART
alexforencich/cocotbext-pcie
PCI express simulation framework for Cocotb
alexforencich/cocotbext-axi
AXI interface modules for Cocotb