cmteric

zhuhai,guangdong,China

Pinned Repositories

ariane
Ariane is a 6-stage RISC-V CPU
Language:SystemVerilog00
block-nvdla-sifive
Language:Verilog0 1 00
Cores-SweRV-EH2
Language:SystemVerilog00
Cores-SweRV-EL2
Language:SystemVerilog0 1 00
curly-duck
test for verilog_obfuscator
Language:Verilog00
e200_opensource
The Ultra-Low Power RISC Core
Language:Verilog00
EDA_FeatureColle
A collection of license features from a varity of EDA vendors
Language:Python00
freedom
Source files for SiFive's Freedom platforms
Language:Verilog00
freedom-e-sdk
Open Source Software for Developing on the Freedom E Platform
Language:C00
ITRI-OpenDLA
Express DLA implementation for FPGA, revised based on NVDLA.
Language:C00

cmteric's Repositories

cmteric/ariane
Ariane is a 6-stage RISC-V CPU
Language:SystemVerilog00
cmteric/block-nvdla-sifive
Language:Verilog0 1 00
cmteric/Cores-SweRV-EH2
Language:SystemVerilog00
cmteric/Cores-SweRV-EL2
Language:SystemVerilog0 1 00
cmteric/curly-duck
test for verilog_obfuscator
Language:Verilog00
cmteric/e200_opensource
The Ultra-Low Power RISC Core
Language:Verilog00
cmteric/EDA_FeatureColle
A collection of license features from a varity of EDA vendors
Language:Python00
cmteric/freedom
Source files for SiFive's Freedom platforms
Language:Verilog00
cmteric/freedom-e-sdk
Open Source Software for Developing on the Freedom E Platform
Language:C00
cmteric/ITRI-OpenDLA
Express DLA implementation for FPGA, revised based on NVDLA.
Language:C00
cmteric/learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
cmteric/Learning-NVDLA-Notes
NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:junning.wu@ia.ac.cn
1 0
cmteric/opene906
OpenXuantie - OpenE906 Core
cmteric/Piccolo
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
Language:Verilog
cmteric/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
Language:Verilog
cmteric/pulpino
An open-source microcontroller system based on RISC-V
Language:C
cmteric/RCNN-NVDLA-SJTU-DEMO
NVDLA Shanghai Jiaotong Univerity DEMO using RCNN. C++ and Python implementation for embedded system.
cmteric/redtail
Perception and AI components for autonomous mobile robotics.
cmteric/ribsnetwork
Language:JavaScript1 0
cmteric/riscv
Language:SystemVerilog
cmteric/riscv-formal
RISC-V Formal Verification Framework
Language:Verilog
cmteric/riscv-openocd
Language:C2 0
cmteric/riscv-tools
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
Language:Shell
cmteric/rocket-chip
Rocket Chip Generator
Language:Scala2 0
cmteric/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Language:SystemVerilog
cmteric/sw
NVDLA SW
cmteric/tiny-dnn
header only, dependency-free deep learning framework in C++11
Language:C++