As shown in the table below. Given the skeleton clock as clk, IMem and DMem will use clk as clock; PC and Register will divide the clk by four as their own clock.
| Component | Clock |
|---|---|
| PC | ~clk/4 |
| IMem | clk |
| Register | ~clk/4 |
| DMem | clk |
With q_imem as input, decoding can be expressed as steps below:
- Decode operation type: decide which instruction will be excuted.
rt = q_imem[16:12],rs = q_imem[21:17],rd = q_imem[26:22]andImmed = q_imem[16:0]are decoded for register and alu operations.ALU_op = q_imem[6:2]andshamt = q_imem[11:7]are decoded if the operation type is decided as alu in step 1, otherwise they will be decoded as 0.
Here, we treat overflow as an exception. Overflow Label which indicate what operation causes overflow will be writtend into $30. Exceptions writing takes precedent in our design.
We use muxes to select the next pc. A few options include T, PC + 1 and PC + N + 1, details are in the processor.v.