coderalai

coderalai's Stars

• plctlab/writing-your-first-riscv-simulator

  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料

  19942

• qemu/qemu

  Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

  Language:C10.7k5.7k

• lazyparser/becoming-a-compiler-engineer

  编译器入门课程的配套教学资料

  65785

• cccriscv/RISCV-Simulator

  RISCV Simulator. Contains single cycle simulator, multiple cycle simulator and pipeline simulator.

  Language:C++32

• mit-pdos/xv6-riscv-book

  Text describing xv6 on RISC-V

  Language:TeX684144

• mit-pdos/xv6-riscv

  Xv6 for RISC-V

  Language:C7.4k2.7k

• cccriscv/mini-riscv-os

  Build a minimal multi-tasking OS kernel for RISC-V from scratch

  Language:C41376

• liangkangnan/tinyriscv

  A very simple and easy to understand RISC-V core.

  Language:C1.1k192

• StevenBaby/alinux

  Linux 源码分析

  Language:C5816

• StevenBaby/computer

  计算机科学体系结构的实现

  Language:Python35598

• StevenBaby/onix

  Onix - 操作系统实现

  Language:C774152

• plctlab/riscv-operating-system-mooc

  《从头写一个RISC-V OS》课程配套的资源

  Language:C933233

• plctlab/llvm-project

  PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8

  Language:C++16040

• plctlab/PLCT-Open-Reports

  PLCT实验室的公开演讲，或者决定公开的组内报告

  1.1k157

• powerjg/learning_gem5

  Learning gem5 is a work-in-progress book to help gem5 users get started using gem5.

  Language:Python17868

• jerralph/riscv-vip

  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

  Language:SystemVerilog5830

• tymonx/logic

  CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

  Language:SystemVerilog27459

• chipsalliance/UHDM

  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

  Language:C++20440

• machineware-gmbh/vcml

  A modeling library with virtual components for SystemC and TLM simulators

  Language:C++13735

• gem5/gem5

  The official repository for the gem5 computer-system architecture simulator.

  Language:C++1.8k1.3k

• tangtangcoding/C-C-

  程序员相关电子书资料免费分享，欢迎关注个人微信公众号：编程与实战

  4.7k1.2k

• tangtangcoding/C-CppLearning

  C语言与C++学习

  1.9k318

• RTimothyEdwards/magic

  Magic VLSI Layout Tool

  Language:C504107

• openhwgroup/core-v-verif

  Functional verification project for the CORE-V family of RISC-V cores.

  Language:Assembly469228

• ben-marshall/awesome-open-hardware-verification

  A List of Free and Open Source Hardware Verification Tools and Frameworks

  50149

• VerificationExcellence/UVMReference

  Reference examples and short projects using UVM Methodology

  Language:SystemVerilog254154

• freecores/aes_beh_model

  AES SystemVerilog behavioral model

  Language:SystemVerilog32

• varunnagpaal/Digital-Hardware-Modelling

  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

  Language:VHDL6113

• Liu-Cheng/cycle-accurate-SystemC-simulator-over-ramulator

  An example of using Ramulator as memory model in a cycle-accurate SystemC Design

  Language:C++489

• mariusmm/RISC-V-TLM

  RISC-V SystemC-TLM simulator

  Language:C29073