coderalai

coderalai's Stars

• ARM-software/CMSIS_5

  CMSIS Version 5 Development Repository

  Language:C1.4k1.1k

• prajwalgekkouga/AHB-to-APB-Bridge

  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

  Language:Verilog5114

• Siddhi-95/AHB-to-APB-Bridge-Verification

  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

  Language:SystemVerilog7819

• fjullien/jtag_vpi

  TCP/IP controlled VPI JTAG Interface.

  Language:Verilog6245

• lowRISC/ibex-demo-system

  A demo system for Ibex including debug support and some peripherals

  Language:C5948

• pulp-platform/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog198

• pulp-platform/cva6

  This is the fork of CVA6 intended for PULP development.

  Language:Assembly1734

• cnrv/riscv-soc-book

  关于RISC-V你所需要知道的一切

  54866

• zhengyangliu/simple-gcc-stm32-project

  Language:C94

• psnjk/SimpleCache

  Simple cache design implementation in verilog

  Language:Verilog4114

• ljhsiun2/EllipticCurves_SystemVerilog

  Elgamal's over Elliptic Curves

  Language:SystemVerilog194

• hyperpicc/ecc

  Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)

  Language:Verilog183

• secworks/aes

  Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

  Language:Verilog340126

• eda-lab/AES-based-on-FPGA

  AES-based-on-FPGA developed by verilog.

  Language:Verilog216

• mematrix/AES-FPGA

  AES加密解密算法的Verilog实现

  Language:Verilog6129

• secworks/sha256

  Hardware implementation of the SHA-256 cryptographic hash function

  Language:Verilog32389

• gk2000/SHA256-Verilog

  Verilog code for SHA-256 hashing

  Language:Verilog1

• ahmad2smile/SHA256_Verilog

  Verilog based FPGA Design of SHA256 Simulated on ModelSim

  Language:Verilog207

• pulp-platform/apb_asynch_cdc

  APB asynchronous clock domain crossing

  Language:SystemVerilog3

• pulp-platform/axi_slice_dc

  AXI Dual-Clock FIFO for clock domain crossings (CDC)

  Language:SystemVerilog216

• pulp-platform/pulpissimo

  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

  Language:SystemVerilog393168

• OP-TEE/optee_os

  Trusted side of the TEE

  Language:C1.6k1.1k

• ForrestBlue/cortexm0ds

  Language:Verilog5834

• THU-DSP-LAB/ventus-gpgpu

  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

  Language:Scala65978

• riscvarchive/riscv-cores-list

  RISC-V Cores, SoC platforms and SoCs

  856206

• kendryte/kendryte-doc-standalone-programming-guide

  Kendryte k210 standalone programming guide

  5114

• pulp-platform/udma_i2s

  Language:SystemVerilog512

• amichai-bd/riscv-multi-core-lotr

  RISCV core RV32I/E.4 threads in a ring architecture

  Language:SystemVerilog307

• lowRISC/OpenIP

  Open source IP collection

  Language:SystemVerilog43

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog904151