Projects to work on as practice for writing SystemVerilog HDL!
Implementing a module to use the 7 Segment Display from 1BitSQuared on an Arty A7-35T.
Simple implementation of a spi master with configurable CPOL and CPHA.
TODO:
- add spi receiver (slave)
Various reusable components for FPGA development. Utils include:
- Debouncer
- Monopulser
- Delay (currently called "counter"... should be changed to reflect this).
TODO:
Simple test implementation of pmodOLEDRGB from Digilent. Link to product page.
TODO:
- Make test image an option for synthesis at compile time.
- Implement a RAM to store rewritable data
- Implement frame buffer
- Implement internal frame clock
- Introduce modes for different color depth (8 bit vs. 16 bit color)