cornell-c2s2

Pinned Repositories

butterfly-unit
Language:Verilog2 1 00
c2s2-tape-out-23
Language:Verilog1 2 00
c2s2_bazel_rules
C2S2 FORK of: Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
Language:Starlark0 1 00
C2S2_Digital_TestChip
This is a test chip for the C2S2 Project Team
Language:Verilog1 1 01
c2s2_ip
A general repository for all of C2S2's IP, including testing
Language:Python1 3 323
dove-fw
C2S2's Software Subteam's Firmware for the Dove RISC-V microprocessor, aimed at implementing a match filter
Language:C1 2 00
FFT
Language:Verilog1 1 01
fixedpt-iterative-complex-multiplier
Language:Verilog0 1 00
fixedpt-iterative-multiplier
Language:Verilog0 1 00
tape_in_sim_mar_23
Language:Python3 1 02

cornell-c2s2's Repositories

cornell-c2s2/tape_in_sim_mar_23
Language:Python3 1 02
cornell-c2s2/butterfly-unit
Language:Verilog2 1 00
cornell-c2s2/c2s2-tape-out-23
Language:Verilog1 2 00
cornell-c2s2/C2S2_Digital_TestChip
This is a test chip for the C2S2 Project Team
Language:Verilog1 1 01
cornell-c2s2/c2s2_ip
A general repository for all of C2S2's IP, including testing
Language:Python1 3 323
cornell-c2s2/dove-fw
C2S2's Software Subteam's Firmware for the Dove RISC-V microprocessor, aimed at implementing a match filter
Language:C1 2 00
cornell-c2s2/FFT
Language:Verilog1 1 01
cornell-c2s2/C2S2-PacketRoutingInterconnect
Language:Verilog0 1 00
cornell-c2s2/dsp
Digital Signal Processing Library from C2S2 Software subteam
Language:C00
cornell-c2s2/Analog_FA23_SP24
2 0
cornell-c2s2/C2S2-Module-Library
Language:Verilog1 0
cornell-c2s2/C2S2-SERDES
Language:Verilog1 01
cornell-c2s2/c2s2-toolchain
C2S2's development environment for package management and reproducibility
Language:Python3 5
cornell-c2s2/C2S2_Analog_TestChip
This is an analog test chip for the C2S2 Project Team
Language:Verilog1 01
cornell-c2s2/c_cxx_training
The is the practice repository for C2S2's C/C++ Training
cornell-c2s2/chip_code_test
Test repository to compile complicated C/C++ programs and simulate within OpenLANE
Language:Verilog1 0
cornell-c2s2/Cocotb_Wb_Full_Chip_Demo
Language:Verilog2 0
cornell-c2s2/crash_detector
Language:C++1 0
cornell-c2s2/ece5745_sec7
Section 7: OpenLANE Open-Source Flow from C2S2
Language:Python1 0
cornell-c2s2/ece5745_testing
Tests and flashing code to test the ECE5745 SP22 chip
Language:Python2 0
cornell-c2s2/FFT_macro
https://caravel-user-project.readthedocs.io
Language:Verilog1 0
cornell-c2s2/magic
Magic VLSI Layout Tool Development for Alignment
Language:C1 0
cornell-c2s2/march24_tapein
Language:Verilog2 0
cornell-c2s2/tape_in_1_2024
Language:Verilog2 0
cornell-c2s2/tape_in_2_2024
Language:Verilog
cornell-c2s2/tape_in_feb_23
Language:Verilog1 0
cornell-c2s2/tape_in_mar_23
Language:Verilog2 0
cornell-c2s2/tape_in_mar_24
Language:Verilog3 0
cornell-c2s2/tape_in_May_FL
Language:Python2 0
cornell-c2s2/Tool-Macros
Script macros to assist with RTL design
Language:Python1 0