[Op][Binding] GetBit/Slice op result must be signless-integer-like

[chhzh123]

When generating getbit/slice op for unsigned integer, we get the following error. (test_compute_pack_unpack.py/test_unpack)

error: 'hcl.get_slice' op result #0 must be signless-integer-like, but got 'ui4'

This is caused by incorrect unsigned type declaration in Python binding.

[chhzh123]

But I got a new error:

module {
  func @top(%arg0: memref<10xi4>) -> memref<2xi1> attributes {bit, extra_itypes = "u", extra_otypes = "u"} {
    %0 = memref.alloc() {name = "B", unsigned} : memref<2xi1>
    %1 = hcl.create_loop_handle "i0" : !hcl.LoopHandle
    affine.for %arg1 = 0 to 2 {
      %3 = memref.alloc() {name = "unpacked_B", unsigned} : memref<1xi1>
      %c0 = arith.constant 0 : index
      %false = arith.constant {unsigned} false
      affine.store %false, %3[0] {to = "unpacked_B", unsigned} : memref<1xi1>
      %c4_i32 = arith.constant 4 : i32
      %4 = arith.index_cast %c4_i32 : i32 to index
      %5 = arith.remsi %arg1, %4 : index
      %c1_i32 = arith.constant 1 : i32
      %6 = arith.index_cast %c1_i32 : i32 to index
      %7 = arith.muli %5, %6 : index
      %c1_i32_0 = arith.constant 1 : i32
      %8 = arith.index_cast %c1_i32_0 : i32 to index
      %9 = arith.addi %7, %8 : index
      %10 = affine.load %arg0[%arg1] {from = "A", unsigned} : memref<10xi4>
      %c1_i32_1 = arith.constant 1 : i32
      %11 = arith.index_cast %c1_i32_1 : i32 to index
      %12 = arith.subi %9, %11 : index
      %13 = hcl.get_slice(%10 : i4, %12, %7) {unsigned} -> i4
      %c0_2 = arith.constant 0 : index
      %14 = affine.load %3[0] {from = "unpacked_B", unsigned} : memref<1xi1>
      %c0_3 = arith.constant 0 : index
      %c0_4 = arith.constant 0 : index
      hcl.set_slice(%14 : i1, %c0_3, %c0_4, %13 : i4)
      affine.store %14, %3[0] {to = "unpacked_B", unsigned} : memref<1xi1>
      %c0_5 = arith.constant 0 : index
      %15 = affine.load %3[0] {from = "unpacked_B", unsigned} : memref<1xi1>
      %16 = affine.load %3[0] {from = "unpacked_B", unsigned} : memref<1xi1>
      affine.store %16, %0[%arg1] {to = "B"} : memref<2xi1>
    } {loop_name = "i0", stage_name = "B"}
    %2 = hcl.create_stage_handle "B" : !hcl.StageHandle
    return %0 : memref<2xi1>
  }
}

python3: /scratch/users/hc676/llvm-project/llvm/lib/IR/Instructions.cpp:2754: static llvm::BinaryOperator* llvm::BinaryOperator::Create(llvm::Instruction::BinaryOps, llvm::Value*, llvm::Value*, const llvm::Twine&, llvm::Instruction*): Assertion `S1->getType() == S2->getType() && "Cannot create binary operator with two operands of differing type!"' failed.

[zzzDavid]

Yes I'm seeing the same error, but it doesn't say which binary op has different operand types

[chhzh123]

Probably the issue of HCLToLLVM pass? I don't see many binary ops here.

python3: /scratch/users/hc676/llvm-project/llvm/lib/IR/Instructions.cpp:2754: static llvm::BinaryOperator* llvm::BinaryOperator::Create(llvm::Instruction::BinaryOps, llvm::Value*, llvm::Value*, const llvm::Twine&, llvm::Instruction*): Assertion `S1->getType() == S2->getType() && "Cannot create binary operator with two operands of differing type!"' failed.
 #0 0x00007f342b0ad38f PrintStackTraceSignalHandler(void*) Signals.cpp:0:0
 #1 0x00007f342b0aadb9 SignalHandler(int) Signals.cpp:0:0
 #2 0x00007f3447d94630 __restore_rt sigaction.c:0:0
 #3 0x00007f34479ed387 raise (/lib64/libc.so.6+0x36387)
 #4 0x00007f34479eea78 abort (/lib64/libc.so.6+0x37a78)
 #5 0x00007f34479e61a6 __assert_fail_base (/lib64/libc.so.6+0x2f1a6)
 #6 0x00007f34479e6252 (/lib64/libc.so.6+0x2f252)
 #7 0x00007f342c544b7b bool llvm::isa<llvm::ConstantInt, llvm::Constant*>(llvm::Constant* const&) (.isra.607.part.608) Instructions.cpp:0:0
 #8 0x00007f342f4cafa2 (/home/hc676/hcl-dialect-prototype/build/tools/hcl/python_packages/hcl_core/hcl_mlir/_mlir_libs/libHCLMLIRAggregateCAPI.so.14+0x3c2cfa2)
 #9 0x00007f342c81a09e convertOperationImpl(mlir::Operation&, llvm::IRBuilderBase&, mlir::LLVM::ModuleTranslation&) LLVMToLLVMIRTranslation.cpp:0:0
#10 0x00007f342d23271f mlir::LLVM::ModuleTranslation::convertOperation(mlir::Operation&, llvm::IRBuilderBase&) (/home/hc676/hcl-dialect-prototype/build/tools/hcl/python_packages/hcl_core/hcl_mlir/_mlir_libs/libHCLMLIRAggregateCAPI.so.14+0x199471f)