high-level-synthesis
There are 121 repositories under high-level-synthesis topic.
google/xls
XLS: Accelerated HW Synthesis
JulianKemmerer/PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
spcl/dace
DaCe - Data Centric Parallel Programming
calyxir/calyx
Intermediate Language (IL) for Hardware Accelerator Generators
NNgen/nngen
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
cornell-zhang/heterocl
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing
PyHDI/veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
spcl/gemm_hls
Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
definelicht/hlslib
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
changwoolee/lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
ferrandi/PandA-bambu
PandA-bambu public repository
HackerFoo/poprc
A Compiler for the Popr Language
spcl/hls_tutorial_examples
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
cornell-zhang/allo
Allo: A Programming Model for Composable Accelerator Design
cucapra/dahlia
Time-sensitive affine types for predictable hardware generation
arc-research-lab/CHARM
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
polyphony-dev/polyphony
Polyphony is Python based High-Level Synthesis compiler.
ymherklotz/vericert
A formally verified high-level synthesis tool based on CompCert and written in Coq.
cornell-zhang/HiSparse
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
cornell-zhang/GraphLily
A graph linear algebra overlay
hlslibs/hls_tutorials
Tutorials on HLS Design
cornell-zhang/hcl-dialect
HeteroCL-MLIR dialect for accelerator design
spcl/apfp
FPGA acceleration of arbitrary precision floating point computations.
benjmarshall/hlsclt
A Vivado HLS Command Line Helper Tool
ic-lab-duth/NoCpad
HLS for Networks-on-Chip
FedericoSerafini/HLS-CNN
High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
osmhpi/metalfs
Near-storage compute aware file system and FPGA operator pipelines.
max2ma/BlackScholes_MonteCarlo
Monte Carlo Methods applied to the Black-Scholes financial market model
RipperJ/FADO
[FPGA 2023] FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs
admk/soap
:dart: soap - Structural Optimisation of Arithmetic Programs
ic-lab-duth/FusedGCN4HLS
Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
arc-research-lab/AIM
AIM: Accelerating Arbitrary-precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP (Full Paper accepted to ICCAD2023)!
IT302/cho
CHO is a benchmark suite for OpenCL FPGA Accelerators
ic-lab-duth/Fast-Float4HLS
Fast Floating Point Operators for High Level Synthesis
UCLA-SEAL/HeteroGen
HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)
wvangansbeke/High-Level-Synthesis
Convert C files into Verilog