high-level-synthesis
There are 123 repositories under high-level-synthesis topic.
HLS-Cryptography-Accelerator
A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer
DaCH
DaCH: dataflow cache for high-level synthesis.
HLS_NoC
HLS code for Network on Chip (NoC)
HLS_for_CNN
This repo has codes for hardware accelerator design for CNNs using high level synthesis from Altera.
HLS_BLSTM
The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))
bream
Bream is a subset/dialect of Scheme that is compiled to run on an alternative platform. More details & initial sources will follow soon.
fold
high abstraction synthesis
DRIM4HLS
DUTH RISC V Microprocessor for High Level Synthesis
HLS_hls4ml_Tutorial
HLS & hls4ml Tutorial
anyhls
High-Level Synthesis with Partial Evaluation
flower
A Comprehensive Dataflow Compiler for High-Level Synthesis
hls-crypto
FPGA Cryptography for High-Level Synthesis
High-Performance-Karatsuba-Multiplier-HLS-FPGA
Implement High-Performance Karatsuba Multiplier in High-Level Synthesis (HLS) for FPGA Based on Recursive Template
HLS_FFT
Design of High-Level Synthesis of Xilinx FFT IP core via FFT library
nbody_hls
Implementation of the N^2-formulation of N-body simulation with Vivado HLS for SDAccel platforms.
db4hls
Repository of DB4HLS. A database of design space exploration in high-level synthesis.
stencil_hls
Implementation of time and space-tiled stencil in Vivado HLS.
Hardware-Software-SHA-3-HLS
HLS SHA-3 Accelerator
visual-system-integrator
Visual System Integrator - Accelerate your embedded development
legup-tuner
Autotuning High-Level Synthesis for FPGAs, published @ ReConFig '17
svpp
Mixing HLS and Backend Versions in Vitis
DP-HLS
HLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA
blake3-fpga
BLAKE3 on FPGA
fuzzing-hls
Finding bugs in high-level synthesis tools using Csmith to generate random, valid C programs.
flames
Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
MSOC2020
Multimedia SoC design (2020 Fall)
zynq-axi-tutorial
A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)
legacy-dynamatic
NOTE: this repository is obsolete, please checkout https://github.com/EPFL-LAP/dynamatic. A fork of the Dynamatic HLS compiler from https://github.com/lana555/dynamatic
Vitis_High_Level_Synthesis_Training
Vitis High Level Synthesis Introduction