/Zynq_HLS_DDR_AXI_IPs_Multiple_Clock

Primary LanguageVHDL

Zynq_HLS_DDR_AXI_IPs_Multiple_Clock

This is a project integrating IP and CortexA9 on Zynq. This CPU-FPGA project with IP cores in different clock domains, for Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation. Compared with the DDR test implemented in here and an application of matrix multiplication here, this project implements a practical project, with IP cores in different clock domains, for Matrix Multiplication, including data generation, FPGA acceleration and result checking.

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Vivado IPs part:

  1. Please firsr import the Vivado projects (2mm_freqChange) and the source code can be found here and HLSTimer, the source code can be found here)
  2. Synthesis them and export them as IPs

Vivado Project part:

  1. Please import the Vivado project (ZedBoard_HLS_kernel_2mm.hw)
  2. Add IP repository which includes the exported HLS IPs and refresh IP catalog
  3. Generated the bitstream and export the hardware to local project
  4. Launch SDK via Vivado

Xilinx SDK part:

  1. please refer to ug871-vivado-high-level-synthesis-tutorial.pdf (Chapter 10)
  2. you can find the source code for Cortex A9 in the directory (https://github.com/zslwyuan/Zynq_HLS_DDR_AXI_IPs_Multiple_Clock/tree/master/HLSMultiIPDiffClock_0907/HLSMultiIPDiffClock_0907.sdk/clockChange). The main function is in the file helloworld.c. More details are described in the comments in the source code.

Very Detailed Instruction:

please refer to ug871-vivado-high-level-synthesis-tutorial.pdf (Chapter 10)